Optical telecommunications network

ABSTRACT

A packet carried on an optical network is routed by carrying out a logic operation on an address word carried in a packet header and a predetermined discriminator word. A routing decision is made in accordance with the result of the logic operation. The logic operation may be a bit-wise Boolean AND operation. An additional logic operation may be carried out with an additional discriminator word to determine whether the packet is destined for a remote region of the network. In this case, the packet may be steered directly to the remote region.

BACKGROUND TO THE INVENTION

The present invention relates to an optical telecommunications network,and a method of routing packets carried on such a network.

Conventionally, telecommunications networks, whether based on copperwires or optical fibres, have been organised on the basis of theprovision of circuits between customers--either semi-permanent "private"circuits or temporary "dial-up" circuits. Until recently, the trafficcarried by such circuits comprised primarily voice telephony togetherwith some low-speed data traffic. Although the replacement of copperfibre networks with optical fibres has provided higher transmissionbandwidths and opened the way to the use of the network for highdata-rate transmissions and services such as video telephony, hithertonetwork resources have been allocated to such services still on thebasis of circuit provisions. However this approach becomes increasinglyinadequate in terms of efficiency of use of the available bandwidth, andnetwork load management, as the traffic carried becomes increasinglybursty, wide-ranging and rapidly fluctuating in bandwidth requirement,with widely diverse message destinations and low predictability. Inparticular, under these conditions, it becomes increasingly difficult tomanage centrally the allocation of specific transmission routes torespective circuit connections.

The paper by Bononi et al. published at pp 2166-2176, Journal ofLightwave Technology, Vol. 11, No. 12, December 1993 discloses a methodof routing packets on an optical network based on header recognition.The header of an incoming packet is demultiplexed using an optical ANDgate and converted into the electrical domain by photodetectors. Theheader is then processed in the electrical domain and a routing decisionmade based on recognition of the address carried in the header. Sincethis operation is carried out in the electrical domain and involvescomplex logical operations on lengthy multi-bit addresses, the switchingoperation is necessarily slow, and potentially represents a seriousbottleneck in the optical network.

The papers by Islam et al. published in IEEE Journal of QuantumElectronics 27(3) 843-848 (1991) and Journal of Lightwave Technology11(12) 2182-2190 (1993) describe a ring network in which logicoperations are carried out on packet headers in the optical domain usingsoliton-based fibre logic gates. Although this avoids some of thebandwidth limitations of the Bononi system, the system again relies uponaddress recognition as the basis of the routing decision. In the exampledescribed, the routing decision is limited to determining whether or nota given packet carries the local address of the node, and so the moduleis not able to route intelligently packets not addressed to that node.Even this limited routing ability requires the processing of a fulladdress, and more complex routing decisions would require the storingand processing of many such addresses.

The paper by Prucnal et al, published in Optical Engineering 29(3)170-182 (1990) discloses an optical routing controller which, as in theprior art systems discussed above, relies upon address recognition. Thecontroller reads destination addresses and appropriately sets a photonicswitch using an optical look-up table. That look-up table has to carryas many header words as there are addresses on the network, and so for arealistically large network is likely to be undesirably complex instructure and operation.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda method of routing a packet at a routing node on an optical networkincluding carrying out in the optical domain a logic operation on anaddress word carried in a packet header characterised in that the saidlogic operation is carried out on the address word and a discriminatorword chosen from a set of discriminator words smaller in number than theset of address words for the network or domain of the network in whichthe said node is located.

The present invention provides a method of routing a packet which makespossible an intelligent decision on the onwards path of a packet from agiven node without requiring recognition of the packet address. Inmaking a decision on onwards, routing of a packet, instead of comparingthe header with an address, or one of a set of words mapping one-to-oneto the network addresses, the present invention uses a discriminatorword chosen to discriminate between the group of addresses for which oneonwards routing direction is appropriate, and the addresses for whichanother onwards routing direction is appropriate. This eliminates theneed for large look-up tables of addresses at the node, or for complexlogic operations, and allows efficient routing using nodes of very lowfunctional complexity.

The invention facilitates the use of a network in which, instead ofrouting paths being determined centrally, each packet finds its own waythrough the network. The network thereby provides connectionlesstransport for the packets i.e. transport not requiring a fixed circuitor path to be established between source and destination. The networkwill typically have a relatively large number of switches or nodes wheretraffic steering or processing can take place. A network configured inthis fashion might comprise, for example, a dual bus or dual ring withtwo counter-propagating traffic streams. The switch or node would thendetermine which of the two directions of propagation would take a givenpacket more quickly to its destination.

The logic operation may comprise two or more individual Booleanoperations on different respective discriminator words. The logicoperation preferably is a bit-wise AND operation.

Preferably the method further comprises carrying out an additional logicoperation on the address word and on a respective additionaldiscriminator word thereby determining whether the packet is addressedto a remote region of the network, and when the packet is so addressedrouting the packet directly towards the said region.

Considering again the example of a dual ring network, the node may insome cases find that the address carried in the header of the packet isfor a destination on the far side of the ring. Then, rather than sendthe packet off on its way step-by-step around the circumference of thering, it is more effective to steer the packet directly onto a linkconnecting opposite sides of the ring, thus bringing the packet morequickly towards its destination. This idea may be extended by theintroduction of further links to provide a topology which is more highlyinterconnected than a simple ring.

Preferably the header of each packet includes an address comprising aplurality of address words corresponding to different sub-fields of theaddress. Preferably the different sub-fields correspond to differentrespective levels of a hierarchy of addresses, an address at one levelcorresponding to a domain encompassing a plurality of addresses at thenext respective level, and so on.

The addresses in the packet headers may be encoded using the sub-set ofbinary words for which word recognition can be carried out by a simpleAND operation, as described and claimed in our co-pending Internationalpatent application PCT/GB94/00397.

According to a second aspect of the present invention, there is provideda node for routing a packet carried on an optical network, characterisedby a routing decision unit arranged to carry out in the optical domain alogic operation on an address word carried in the header of the packetand a predetermined discriminator word, and a switch responsive to therouting decision unit and arranged to route the packet in differentdirections depending on the result of the said logic operation.

Preferably the routing decision unit includes one or more optical ANDgates.

According to a third aspect of the present invention, there is providedan optical network comprising a plurality of nodes, each node having adifferent respective address, and each node including a routing decisionunit arranged to carry out a logic operation on an address word carriedin the header of a packet carried by the network, characterised in thateach said routing decision unit is programmed with a discriminator wordchosen from a set of discriminator words smaller than the number ofaddress words and is arranged to carry out the said operation on saidaddress word and the respective discriminator word.

Preferably the network may be a dual-bus or ring network, oralternatively a two-dimensional network such as a 2-connected network,and in this case preferably is picket fence network, as defined herein.

In multi-gigabit optical transmission networks, a key design aspect ishow to maintain proper time synchronisation of the various signalprocessing and switching equipments across the network. In opticaltime-division multiplexed (OTDM) networks, accurate bit-level timinginformation is needed at the network nodes to carry out operations suchas demultiplexing and drop-and-insert of OTDM channels. However, in OTDMthe transmission links between network nodes carry continuous bitstreams, and so the bit-level timing information can be extracted usingclock recovery based on phase-locked loops (such as microwave electronicclock recovery or all-optical clock recovery). On the other hand, inultrafast asynchronous packet networks, where the bit streams are brokenup into short bursts (packets), a different approach is needed.

According to a fourth aspect of the present invention there is provideda method of processing a packet carried on an optical networkcharacterised by using both a global packet-level clock and a localbit-level clock.

DESCRIPTION OF THE DRAWINGS

Systems embodying the present invention will now be described in furtherdetail, by way of example only, with reference to the accompanyingdrawings in which:

FIG. 1 shows a dual bus network;

FIG. 2 shows an example of a node for use in the network of FIG. 1;

FIGS. 3a and 3b are logic diagrams for a three node network using twoalternative address schemes;

FIGS. 4a to 4d are logic diagrams for nodes 2 to 5 of a 6-node dual busnetwork;

FIGS. 5a to 5h are logic diagrams for nodes 2 to 9 of 10-node dual busnetwork;

FIGS. 6a to 6r are logic diagrams for nodes 2 to 19 of a 20-node dualbus network;

FIG. 7 is a circuit diagram for one of the decision logic units of FIG.2;

FIG. 8 shows a 6-node ring network;

FIGS. 9a and 9b are logic diagrams for nodes 1 and 6 of the network ofFIG. 8;

FIG. 10 shows a 6-node ring network including a cross-link between nodes2 and 5;

FIGS. 11a and 11b are logic diagrams showing the modified decision logicfor nodes 2 and 5;

FIG. 12 shows a modified decision logic diagram for node 3 in thenetwork of FIG. 10;

FIG. 13 is a diagram illustrating the address structure of a packetcarried on a network embodying the present invention;

FIG. 14 shows a two-tier cross-linked ring network having six addressdomains;

FIG. 15 is an overview of a telecommunications network incorporating thering network of FIG. 8;

FIG. 16 shows a network time slot;

FIG. 17 shows a circuit for recovery of a packet-level clock;

FIG. 18 shows a binary routing node;

FIG. 19 shows in further detail the circuit of FIG. 18;

FIG. 20 shows an SLA AND gate gated by a network clock;

FIG. 21 shows a Manhattan Street (MS) network topology:

FIG. 22 shows a picket fence (PF) topology;

FIG. 23 shows a close-woven PF topology; and

FIG. 24 shows a clock-recovery/demultiplexer circuit.

DESCRIPTION OF EXAMPLES

A high-speed optical telecommunications network 1 is formed frommonomode optical fibres (F). As shown in FIG. 15, the network isconnected via nodes n1, n2 . . . to access circuits 2 arranged to carryout packet generation and packet decompression. The access nodes 2receive incoming lower-speed data channels and packetise the data toform short fixed-length packets or cells. These packets may use, forexample, an ATM frame structure. They include, in the optical header,data indicating the destination address for the respective packet. Inthis first example, the network has a dual bus structure, as shown infurther detail in FIG. 1. One bus carries packets propagating in onedirection, and the other bus packets propagating in the oppositedirection. Each node, other than those at the extreme ends of thenetwork includes a routing decision circuit incorporating one or moreoptical AND gates. Using this circuit, each node ANDs a few short wordsor fragments of words from the address field of a packet with a fixedpredetermined discriminatory word or words characteristic of theparticular node, and switches its output to put the packet on one orother of the two buses as appropriate. As a simple example, if theaddress is determined to be one of the next few nodes in the forwarddirection of the bus, then the routing decision circuit will direct thepacket onto the one of the two buses carrying forward-propagatingtraffic. Similarly if it were one of the immediately preceding nodes,then the packet would be output onto the other of the two buses.

As described in further detail below, the routing decision operationrequires only a simple optical AND logic, and similarly an AND operationis used at each node for address recognition. In the present embodiment,the binary address words for the packets are chosen from the restrictedset of n-bit words satisfying the property that for any two words A=a₁a₂ . . . a_(n) and B=b₁ b₂ . . . b_(n) in the set, AxB=0 only if A=B,otherwise AxB=1 where AxB denotes the Boolean expression ##EQU1## and xdenotes the logical complement of x. The use of this set of binary wordsfor word recognition is described and claimed in the present applicant'sco-pending international application WO94/21088. As discussed in thatapplication, the maximum possible number of n-bit words within the set,assuming n is an even number, comprises n|/ (n/2)|!² words consisting ofn/2 ones and n/2 zeros in all permutations. For n odd, there are twoequal-sized and mutually exclusive maximum sets each comprising n|/{(n+1)/2!| n-1)/2!|} words; one set contains words consisting of (n+1)/2ones and (n-1)/2 zeros in all permutations, and the other set isobtained from the first by interchanging zeros and ones.

Using this restricted set of words, address recognition is then carriedout using an optical AND operation of the form AxB. By contrast, thepacket routing uses AND operations of the form AxB as defined below.While the use of the restricted word-set is preferred since itsimplifies the address recognition stage, the use of this restrictedword-set is not essential to the packet routing decision. The operationAxB can be used for routing decision logic even where A and B are notfrom the restricted word-set.

Using this restricted set, in the case of a network with 20 nodes forexample, the addresses may be denoted by the 20 distinct 6-bit wordsconsisting of three ones and three zeros in all permutations. It isconvenient, but not essential, to allocate addresses to the nodes alongthe bus in ascending order of their value as binary numbers (in thisexample, starting with 000111 and ending with 111000).

FIG. 2 shows a possible layout for an ith node on the dual bus networkof FIG. 1. The same structure may be used also in a dual ring network asin the embodiments described below.

Packets arriving from adjacent nodes (i-1) and (i+1) on the bus areexamined by node i address recognition units. These carry out an ANDoperation on the address carried by the packet together with a targetword corresponding to the address of the node in the manner described inour above-cited international application. If this operation indicatesthat the address carried by this packet is that of this node (node i),so that the packet is destined to leave the bus via this node, then the1×2 routing switch associated with the respective address recognitionunit is set accordingly to direct the packet onto an output routeleading away from the bus. All other packets arriving from adjacentnodes and not destined to exit via this node are directed onwards to adecision logic unit and output contention resolution module. Packetsentering the network at this ith node are merged into the traffic streamgoing to the decision logic unit and contention resolution module.

The output contention resolution module performs the task of routingeach outgoing packet towards the appropriate one or other of theadjacent nodes, whilst ensuring that no two packets are directed to thesame output simultaneously. The decision logic unit determines which ofthe two outgoing routes is the appropriate one for each packet, andinstructs the output contention resolution module accordingly. Ifcontention cannot be resolved, one or more packets is diverted onto the"wrong" route, travels to the next node in the "wrong" direction, andthere is rediverted to the correct route.

The output contention resolution module may be for example the devicedescribed by D. K. Hunter and I. Andonovic (Elec. Letts. 29, 280-281,1993). It is a switch fabric consisting of a sequence ofelectrically-controlled 2×2 optical switches and optical delay lines.The optical switches may be, for example, lithium niobate devices typeY-35-8772-02 supplied by GEC Advanced Optical Components, or 2×2integrated InP semiconductor devices of the type described by G.Sherlock et al (Elec. Letts 30, 137-138, 1994). Since the optical delaysrequired in the contention resolution module are integer numbers of thepacket period (typically 1 ns or longer), the delay lines in this casemay be made from appropriate lengths of optical fibre. The merge unitsshown in FIG. 2 may comprise circuits of the form described in ourco-pending application EP 94306015.2. These use the same opticaltechnology as the output contention resolution module. The divider unitmay be an electrically-controlled 1×2 optical switch (alternatively the2×2 devices mentioned above would be satisfactory) arranged to sendpackets to one of its two outputs alternately. This has the effect oftending to balance the additional traffic load on each of the two inputsto the contention resolution module. This is not an essential featurebut is advantageous under some traffic conditions.

The functioning of the decision logic units will now be described infurther detail. FIGS. 3 to 6 show the decision logic for a dual busnetwork with nodes having 3-bit, 4-bit, 5-bit and 6-bit addressesrespectively. FIG. 7 illustrates an appropriate hardware implementationof a decision logic unit.

FIG. 3 shows the decision logic required for the simple case of a dualbus network having just three nodes. In FIG. 3a, it is assumed that theaddresses of the nodes are represented by a 3-bit word H=h₁ h₂ h₃consisting of 1 one and 2 zeros in all permutations and arranged alongthe bus in the sequence of ascending binary value 001, 010 and 100 asshown in Table 1 below.

                  TABLE 1    ______________________________________            Node Address    ______________________________________            1    001            2    010            3    100    ______________________________________

No decision logic is required for node 1 (address 001) or node 3(address 100) because they are situated at the ends of the bus--in otherwords there is only one route for outgoing traffic from each of thesenodes. At node 2 (address 010) a decision must be made as to whetheroutgoing packets should travel towards node 1 or node 3. The appropriatedecision logic for node 2 is shown in FIG. 3a. In this figure andelsewhere we use the notation ##EQU2## where A and B are n-bit words,A=a₁ a₂ . . . a_(n) and B=b₁ b₂ . . . b_(n). In FIG. 3 for example,Hx100 means h₁ ·1+h₂ ·0+h₃ ·0=h₁.

Alternatively, the address scheme with 3-bit address words consisting of2 ones and 1 zero in all permutations, as set out in Table 2 below,could be used. In that case, the decision logic for node 2 is as shownin FIG. 3b. In both cases, the predetermined discriminator word used inthe decision logic is 100, but the different outputs are mappeddifferently to the logic values produced by the operation depending onthe address scheme used.

                  TABLE 2    ______________________________________            Node Address    ______________________________________            1    011            2    101            3    110    ______________________________________

FIG. 4 shows the decision logic required for the case of a dual busnetwork having 6 nodes with the addresses of the nodes represented by a4-bit word H=h₁ h₂ h₃ h₄ consisting of 2 ones and 2 zeros in allpermutations, arranged along the bus in sequence of ascending binaryvalue.

                  TABLE 3    ______________________________________            Node Address    ______________________________________            1    0011            2    0101            3    0110            4    1001            5    1010            6    1100    ______________________________________

As before, no decision logic is needed for the end nodes, 1 and 6. Asseen in the figures, in this case node 2 uses the discriminator word1100, nodes 3 and 4 the discriminator word 1000 and node 5 thediscriminator word 0011.

FIG. 5 shows the decision logic required for the case of a dual busnetwork with 10 nodes with the addresses of the nodes represented by5-bit words consisting of 2 ones and 3 zeros in all permutationsarranged along the bus in the sequence of ascending binary value.

                  TABLE 4    ______________________________________            Node Address    ______________________________________            1    00011            2    00101            3    00110            4    01001            5    01010            6    01100            7    10001            8    10010            9    10100            10   11000    ______________________________________

As before, no decision logic is needed for end nodes 1 and 10. It willbe seen that in this case, some of the nodes require two discriminatorwords and a corresponding pair of logic operations to make the binaryrouting decision. This is the case, for example, for node 5 (address01010). As in the case with n=3 (FIG. 3b) an alternative address schemefor 20 nodes could be used, consisting of 5-bit words with 3 ones and 2zeros in all permutations. The decision logic would be then similar tothat shown in FIG. 5.

FIG. 6 shows the decision logic required for the case of a dual busnetwork having 20 nodes with the addresses of the nodes represented by a6-bit word H=h₁ h₂ h₃ h⁴ h₅ h₆ consisting of 3 ones and 3 zeros in allpermutations, arranged along the bus in sequence of ascending binaryvalue.

                  TABLE 5    ______________________________________            Node Address    ______________________________________            1    000111            2    001011            3    001101            4    001110            5    010011            6    010101            7    010110            8    011001            9    011010            10   011100            11   100011            12   100101            13   100110            14   101001            15   101010            16   101100            17   110001            18   110010            19   110100            20   111000    ______________________________________

The discriminator words used in the examples described above and shownin the figures, and discriminator words for other networks havingdifferent numbers of nodes, may be determined by inspection. Forexample, the decision logic for node 7 (address 010110) illustrated inFIG. 6g is derived as follows: (i) inspect the table of node addressesand identify distinct and distinguishing features of addresses of nodesabove and below node 7 (i.e. how are the addresses of nodes 1 to 6clearly distinguishable from the addresses of nodes 8 to 20?); then (ii)devise the minimum number of tests based on operations of the type AxBthat discriminate on the basis of these distinguishing features. In thisexample, the addresses A of nodes 1 to 6 are distinct from nodes 8 to 20in that they (a) begin with 00 (and therefore Ax110000=0) or (b) theybegin with 010 (and therefore Ax101000=0). Conversely the addresses of 8to 20 do not begin with 00 or 010 so Ax110000=1 and Ax101000=1. Thedecision logic for node 7 therefore applies these tests to the header Hof the outgoing packets to determine the correct direction for onwardspropagation.

Each operation AxB requires just one optical AND gate, and as seen inthe above example as few as 2 (or exceptionally 3) operations of thistype are required to handle 20 6-bit node addresses.

FIG. 7 shows one example of a decision logic unit using optical hardwareto perform the operation HxW where H is the address field (or a portionof it) in the header of an incoming packet, and W is a discriminatorword. The operation HxW is performed by the optical AND gate referenced72, together with the photodetector and electronic threshold detectorthat follows it. This optical AND gate 72 is an ultrafast device thatproduces a short optical pulse of picosecond duration at its outputwhenever a short pulse is incident simultaneously at each of its twoinputs. A suitable example, is the semiconductor optical AND gate usingfour wave mixing (FWM) described and claimed in our co-pending Europeanapplication no. 94307188.6. (BT reference A24802) and is disclosed inWO/94/21088. The response of the photodetector does not need to beultrafast, but is fast enough to respond at the packet rate (typically0.1-1 GHz). The electronic threshold detector is set to produce anoutput corresponding to the logical value HxW=1 if the input signalindicates that the photodetector has picked up at least one output pulsefrom the AND gate 72 simultaneously with the arrival of an incomingpacket. If the photodetector does not pick up any output pulse when apacket arrives, this indicates that HxW=0. The word W is created bygenerating a clock pulse in precise synchronism with the incoming packetand then replicating this clock pulse as necessary to create thediscriminator word W. If the word W is a simple one involving just oneor two optical pulses, then it may be sufficient to replicate usingfibre couplers and appropriate lengths of optical fibre. For morecomplex words W it may be preferable to use a silica planar delay linedevice such as described by C. J. Beaumont et al in BTTJ 9, 30-36, 1991.Suitable methods for generating the clock pulse in synchronism with thepacket are described in detail in our co-pending Internationalapplication filed this day entitled `Packet Processing`, Agents ref.80/4850/03. The method adopted in the circuit of FIG. 7 uses abit-asynchronous marker pulse associated with the header of the inputpacket. This is input to an ultrafast optical AND gate 71 with one ofthe inputs to the AND gate passing through a delay line tuned to thebit-asynchronous time difference between the marker pulse and a firstbit of the header, which is always set to have the value 1. This markerpulse and set leading bit are separate from the words H making theheader address operated upon in the address detection and routingdecision stages. As shown in FIG. 7, the clock pulse output from theoptical AND gate 71, is also picked up by a second photodetector and theresulting electrical pulse used as a synchronising signal for thethreshold detector electronics. This optional feature serves to improvethe signal-to-noise performance of the threshold detector by allowingthe circuit to be gated or enabled for a short time period insynchronism with the incoming packet.

FIG. 7 shows a decision unit for the simplest case where there is asingle operation of the form HxW to be carried out. As seen in the logicdiagrams of FIGS. 5 and 6, sometimes the decision unit requires two ormore such operations. In these cases one AND gate is provided for eachof the HxW operations, and simple digital electronic circuitry is usedto complete the logic operations specified in the decision logicdiagram.

Although the examples so far described have used a dual bus network, thepresent invention is by no means limited in this respect and may be usedwith a variety of different topologies. FIG. 8 shows how a dual bus canbe transformed into a ring network by joining the ends. The exampleshown is for a network with 6 nodes and 4-bit addresses. The requireddecision logic is identical to that shown in FIG. 4, except thatdecision logic is now required for nodes 1 and 6, as shown in FIGS. 9aand 9b respectively.

Suppose we have a dual bus or dual ring architecture and that thedecision logic unit in a node determines that a particular packet isaddressed to somewhere far distant along the bus. Then rather thansending the packet off on its way laboriously step-by-step along thebus, it would be more effective to steer the packet directly onto a"short-circuit" link connecting to a position further along the bus andthus bringing the packet more quickly towards its destination.Similarly, if we have a ring architecture and a node in the ringdetermines that a packet is addressed to somewhere on the far side ofthe ring then it would be more effective to steer the packet directlyonto a link connecting opposite sides of the ring. This is illustratedin FIG. 10, which shows the ring network of FIG. 8, but with across-link between nodes 2 and 5. In this case, the decision logic fornodes 2 and 5, although still using the same principles and binarysteering methods, must be modified to allow the selection of 1 from 3possible outgoing routes. The appropriately modified decision logic fornodes 2 and 5 is shown in FIGS. 11a and 11b respectively. We candemonstrate the effect on the traffic of introducing this cross-link bycounting up the number of hops (that is links between nodes) that apacket would have to make with and without the presence of thecross-links. As a simple example, the table below is for the case ofpackets leaving node 2 in the network of FIG. 10, depending on theultimate destination of the packet.

    ______________________________________                Number of hops    Destination node                  Without crosslink                              With crosslink    ______________________________________    1             1           1    2             --          --    3             1           1    4             2           2    5             3           1    6             2           2    ______________________________________

There is a reduction in the number of hops for traffic destined for node5. This has the effect of reducing the traffic load on some of thelinks. However, the redistribution of traffic will be more effective ifwe also change the decision logic for adjacent nodes. FIG. 12 shows amodified decision logic diagram for node 3, but has the effect of movingmore of the traffic leaving node 3 onto the cross-link between nodes 2and 5.

In the examples so far described, the decision logic discussed has allbeen deterministic in nature. However, depending on the traffic loads inthe network, some reconfiguration of the decision logic is desirable inorder to distribute the traffic loads more evenly and to avoid hotspots. For example, in the case of node 3 in the ring network withcross-linking shown in FIG. 10, it is possible to reconfigure thedecision logic diagram from the form shown in FIG. 4b to the form shownin FIG. 12. This can be done using electrically-controlled opticalswitches to bring in different logic units or sub-units. In thisexample, an optical switch could be used to bypass the first decisiongate as shown by the dashed line in FIG. 12. This switch-over may becontrolled by a central network management system. Alternatively, or inaddition, in a network that has some in-built intelligence at the nodes,route selection may be a dynamic process that depends on instantaneouslocal traffic loads, as described for example in EP-A-465 090.

We now consider how the ultrafast optical packet routing techniquesdescribed in the above examples can be extrapolated to provide animplementation for a large-scale network with more irregular geometry.In the simple dual bus or dual ring network, the amount of cross-linkingcan be gradually increased so that the system moves towards a morehighly interconnected mesh. However, this tends to produce acorresponding increase in the complexity of the address routing anddecision logic. Not only does this add undesirably to the complexity ofthe optical and other hardware, but the network then becomesincreasingly inflexible. It may for example be increasingly difficult toadd additional nodes without having to reconfigure the decision logicfor many adjacent nodes.

A network which is scalable without these penalties can be achieved byusing a network hierarchy corresponding to different segments of theaddress field in the packet header. One example of an appropriatestructure for the address header is shown in FIG. 13. In this figure,the marker pulse and first header bit are used only for clocksynchronisation purposes, and are not relevant to the routing/decisionlogic. The remainder of the header may be divided into two or moreaddress sub-fields as shown. Each of the sub-fields is a binary wordpreferably chosen from the special sub-set of binary words definedabove. This allows each individual sub-field to be recognised andprocessed optically using simple optical AND operations in the mannerdescribed above. A further preferred constraint is that the completeaddress taking all the sub-fields together should also be a word fromthe same sub-set of all possible binary words. If the sub-fields are allwords composed of an even number of bits, then this additionalconstraint on the entire header is automatically met. If however morethan one of the sub-fields are composed of an odd number of bits, thencare must be taken to select the coding scheme for each of thosesub-fields (using either i+1 ones and i-1 zeros, or the converse) toensure that the complete address satisfies the coding requirements.

This scheme allows us to introduce a hierarchy of address domains withinthe overall network so that there is a relatively small number ofdistinct addresses within each domain. The address of a domain in eachsuccessive level in the hierarchy is represented by a correspondingaddress sub-field. (This can be likened to the different lines of theaddress on a letter in the postal system--the name of the county, town,street and so on).

FIG. 14 shows an example of a two-tier network in which there are sixaddress domains interconnected by the cross-linked ring network of FIG.10. A node with the address 10100110 could reside in the address domainnumber 5. The address is divided into two 4-bit sub-fields. The firstsub-field (1010) represents the address of node 5 in the ring. Thesecond sub-field (0110) is the address of the node within the addressdomain 5. The table below gives examples of the number of distinctaddresses that can be accommodated for different lengths of the address(excluding marker and timing bits etc).

    ______________________________________                             Number of    Length of  Number and size                             distinct    address field               of sub-fields addresses    ______________________________________    8     bits     Two 4-bits    6 × 6 = 36    10    bits     Two 5-bits    10 × 10 = 100    12    bits     Two 6-bits    20 × 20 = 400    16    bits     Two 6-bits, one                                 20 × 20 × 6 = 2400                   4-bits    18    bits     Three 6-bits  20 × 20 × 20 = 8000    ______________________________________

Each of the addressed ultrafast packet nodes or "feeders" in the outertier of the network, such as the node with address 10100110 may beconnected to a large number of customers via conventionalcircuit-switched channels. The overall network capacity is given by theproduct of the feeder capacity and the number of feeders. For example,2400 feeders (using 16-bit addresses) might serve a national network,providing 60 feeders at each of 40 major population centres. Each feedermight operate at ˜30 Gbit/s payload capacity (100 Gbit/s peak line rateand 50% traffic load, taking into account time guard bands and otheroverheads). The overall network capacity is then ˜2400×30 Gbit/s=72Tbit/s. At any instant, this is sufficient to serve around 750,000customers at an average of 100 Mbit/s (or 7.5 million customers with 10%instantaneous network utilisation per customer). In this example, eachof the population centres would be served by 60 optical fibres, or fewerfibres combined with a modest amount of wavelength-divisionmultiplexing.

One characteristic of this aspect of the present invention is that thenumber of distinct logic operations needed to make a routing decision issignificantly less than the number of bits in the addresses. Table LO1below illustrates this for 3-bit addresses. This extends Tables 1 and 2above.

                  TABLE LO1    ______________________________________    Node Address  No of logic operations    ______________________________________    1        001 or 011                      0    2        010 or 101                      1    3        100 or 110                      0    Average = 0.33    ______________________________________

Next for the case of nodes with 4-bit addresses. This extends Table 3above using FIG. 4.

                  TABLE LO2    ______________________________________    Node Address  No of logic operations    ______________________________________    1        0011     0    2        0101     1    3        0110     1    4        1001     1    5        1010     1    6        1100     0    Average = 0.66    ______________________________________

Next for the case of nodes with 5-bit addresses. This extends Table 4from above using FIG. 5.

                  TABLE LO3    ______________________________________    Node Address  No of logic operations    ______________________________________    1        00011    0    2        00101    1    3        00110    1    4        01001    1    5        01010    2    6        01100    1    7        10001    1    8        10010    2    9        10100    1    10       11000    0    Average = 1.0    ______________________________________

Next for the case of nodes with 6-bit addresses. This extends Table 5above using FIG. 6.

                  TABLE LO4    ______________________________________    Node Address  No of logic operations    ______________________________________    1        000111   0    2        001011   1    3        001101   2    4        001110   1    5        010011   1    6        010101   2    7        010110   2    8        011001   2    9        011010   2    10       011100   1    11       100011   1    12       100101   2    13       100110   2    14       101001   2    15       101010   3    16       101100   2    17       110001   2    18       110010   2    19       110100   1    20       111000   0    Average = 1.55    ______________________________________

The routing method of the present invention offers significantadvantages with 2-connected networks, and in particular with a novelpicket-fence topology developed by the present inventors and describedin further detail below.

Picket Fence Networks

The inventors have devised a new design of network that has significantadvantages for ultrafast packet transmission compared to previousdesigns. It is a `two-connected` network with nodes connected in theform of a picket fence. In a `two-connected` network all the nodes havetwo inputs and two outputs. Probably the best-known example is theManhattan Street (MS) Network N. F. Maxemchuk, "Regular and meshtopologies in local and metropolitan are networks" AT&T Tech. J. vol 64,pp 1659-1686 (Sept 1985), in which the links are arranged in a structurethat resembles the streets and avenues in Manhattan (FIG. 21). The MSnetwork is formed by joining together the two ends of each row andcolumn to create a toroidal structure. The MS network is well suited asa self-routing packet network because there are many alternativeroutings between any pair of nodes, so that contention within thenetwork can be resolved readily by deflecting packets along differentroutes. The nodes in the network determine the optimum onward path forpackets in transit by using `routing rules` or algorithms. However therouting rules for the MS network "Routing in the Manhattan StreetNetwork" IEEE Trans on Communications vol COM-35 no. 5, pp 504-512 (May1987)! require the nodes to determine the full destination address ofeach packet in transit.

We are interested in developing optical packet networks that can operateat very high speed, with the bit-level processing in the network nodescarried out in the optical domain. We therefore need to devise networksthat can operate with very simple routing rules to minimise thecomplexity of optical hardware. For example, the routing rules for theMS network would require serial-to-parallel conversion of the fullpacket headers at ultrafast speed. We would prefer a routing rule basedon logic operations of the type HxW. We have therefore devised a newnetwork design (called the `Picket Fence` network).

Like the MS network, the links in the Picket Fence (PF) network arearranged in a structure that resembles the streets and avenues inManhattan. However, whilst the MS network is formed by joining togetherthe two ends of each row and column, the PF network is formed byconnecting the ends of adjacent rows or columns so as to formbidirectional links at the periphery of the network.

In the form shown in FIG. 22, the network resembles a picket fence,hence the name. Another example, shown in FIG. 23, could be given thename `Close Woven` network because it resembles a fabric woven from asingle continuous thread. At present we use the term `PF Network` forall two-connected networks with nodes on a rectangular grid with theends of adjacent rows or columns connected so as to form bidirectionallinks at the periphery of the network.

The attraction of these PF networks is that efficient routing rules canbe devised that do not require the nodes to determine the fulldestination address of packets in transit.

The simplest routing rule is as follows:

Select the preferred path if there is one preferred path from a node.

Select either path at random if there are zero or two preferred pathsfrom a node.

A preferred path is one which is in a direct line towards the celldestination or lies on the border of the quadrant in which thedestination is situated. A path which is a direct line away from thecell destination is never preferred.

The rule can be implemented by determining only the signs ofΔR=R-R_(DEST) and ΔC=C-C_(DEST), where R and C are the row and columncoordinates of the current node, R_(DEST) and C_(DEST) are the row andcolumn coordinates of the destination node. From the signs of ΔR and ΔC,the quadrant in which the cell destination is situated (relative to thecurrent routing node) and thus the preferred path can be determined. Itis not necessary to know the precise destination address, nor theconfiguration of the destination node, nor the size of the network orother global parameters.

The signs of ΔR and ΔC can be determined optically for ultrafast opticalpackets using the methods described above. The examples worked out abovedescribe logic operations (using `discriminator words`) to determine thepreferred direction of onward propagation for a packet in a dual busnetwork. In effect the logic operations are used to determine whetherthe destination address of the packet is less than or greater than theaddress of the current switching node. This is equivalent to determiningthe sign of relative address of the destination node compared to thecurrent node (i.e. equivalent to determining the sign of ΔR and ΔC in a2-D network). Therefore in the two-dimensional `Picket Fence` networkthe same technique can be used twice at the switching node (once todetermine the relative position of the destination node in the rowdirection using the portion of the packet address field that indicatesthe row number of the destination address, and once to determine therelative position of the destination node in the column direction usingthe portion of the packet address field that indicates the column numberof the destination address). The routing rules are set out in the table"PF Routing" below.

We have carried out extensive numerical performance modelling of PFnetworks (using the Opnet modelling tool). We have determined theefficiency of this basic routing rule and also other slightly morecomplex variants. The results of these simulations indicate that therouting efficiency is good, quite comparable to the well-known MSnetwork, even though the routing rule itself is more simple and easierto implement in ultrafast optics. Moreover when the `hot potato` routingstrategy is used (i.e. no buffering of packets at the routing nodes) insimulations of traffic flow in these networks, the traffic throughputsof the PF and MS networks are quite comparable. This is an importantresult because buffering in the optical domain is difficult and to beavoided. However the simulations have also highlighted that relativeperformance of the PF network is best when traffic loadings are not toohigh.

Hybrid Synchronisation

As discussed in the introduction above, for ultrafast packet networks,there is a key design problem of maintaining synchronisation.

For ultrafast packet networks we propose a "hybrid" synchronisationscheme, comprising a combination of: i) a continuous, global networkclock providing packet-level time information (the precision beingequivalent to many bit periods); ii) localised, packet-specific timeinformation (with precision at the bit level).

This proposal arises from our realisation that in ultrafast packetnetworks, timing information is needed for various purposes on twodifferent time scales: the bit-level time scale (with precisiontypically a few picoseconds or less for packet networks operating at aninstantaneous bit rate of 100 Gbit/s or greater) and a packet-level timescale (with precision typically several bit periods, 50-100 picoseconds,for packet lengths on the order of 1-10 nanoseconds). The ultrafast(picosecond) timing information is needed for localised(packet-specific) optical bit-level processes such as header addressrecognition, self-routing decisions, and demultiplexing; whereas global(network-wide) synchronisation at the packet level is used to definepacket time slots. The main purpose of the global network clock is toensure that packets are properly separated in time so as to avoidcollisions and also so as to allow sufficient time for optoelectronicrouting switches to operate without corrupting packets in transit. Asexplained later, this global, packet-level clock can have other usefulpurposes: for example, to ensure correct time synchronisation of routingswitches throughout the network, to provide signal gating and noisereduction.

We consider it would be very difficult to satisfy these varioussynchronisation requirements using a single (non-hybrid) scheme toprovide a global clock with bit-level timing precision. This is becausein an ultrafast packet network it would be extremely difficult todistribute a clock with bit-level (i.e. picosecond) timing precision andensure that all the packets and switching equipment throughout thenetwork are at all times precisely synchronised to that clock. This isbecause at 100 Gbit/s, for example, the bit period is 10 picoseconds,equivalent to a path length in fibre of just 2 mm. As already mentioned,in OTDM networks a global bit-level clock can be distributed effectivelywith very good precision, despite network path-length variations. Thisis because: i) the circuit routings are fixed (except for infrequentreconfiguration under manual or network management control); and ii) thebit streams are continuous and therefore clock recovery methods based onphase-locked loops can be used. In a packet network, however, this ismuch less practical. Successive packets on a given link may haveoriginated from different sources and have travelled along widelydiffering physical paths before reaching that link, and therefore havebeen subjected to very different transit-time variations.

The synchronisation scheme we have developed for ultrafast packetnetworks is therefore a "hybrid" solution. We combine localisedfine-grain (bit-level) timing extraction on a packet-by-packet basistogether with global coarse-grain (packet-level) timing. FIG. 16 shows,by way of example, a timing diagram for the time slots in an ultrafastpacket network. This diagram illustrates the relationship between thebit-level and packet-level time references. The network clock providesonly coarse network synchronisation at the packet level. The network isthus slotted in time and space, at the clock frequency, with a maximumof one cell occupying each slot. In the example shown in FIG. 16, thetime partitioning within the time slot has been dimensioned toaccommodate standard ATM cells. The network clock has been chosen to beone of the standard SDH rates. The cell consists of a burst ofultrashort optical pulses representing about 440 bits (the 53-byte ATMcell plus around 10-20 additional header bits to allow routing of thecell in the ultrafast optical packet network) at An instantaneous rateof 100 Gbit/s. Notice that the position of the cell within its time slotis not defined with bit-level precision; instead there is a timingtolerance equal to several bit periods (around 100 picoseconds or 10 bitperiods in this example). The network time slot also contains a switchband, allowing time for the reconfiguration of routing switches, andtime guard bands. It is necessary for this switch band to be equivalentto many bit periods. For example, typical routing switches (lithiumniobate devices such as type Y-35-8772-02 supplied by GEC AdvancedComponents, or 2×2 integrated InP semiconductor of the type described byG Sherlock et al in Electronics Letters 30, 137-138, 1994) are capableof switching configuration in a time of ˜1 ns. Therefore for cells withan instantaneous bit rate of 100 Gbit/s, a 1 ns switch band isequivalent to 100 bit periods.

For the reasons described earlier, it is necessary to obtain bit-leveltiming information on a packet-by-packet basis. Several ways of doingthis are discussed in our co-pending International application entitled"Packet Processing" (ref: 80/4850/03), the contents of which areincorporated herein by reference. For example, FIG. 24, corresponding toFIG. 7 of that copending application shows a circuit which recovers abit-level clock from a marker pulse carried with the packet, and usesthat clock in a demultiplexer. In this implementation the AND gate is asemiconductor laser amplifier. The original and delayed versions of thepacket input to the AND gate interact in the SLA by a process of fourwave mixing (FWM). Independent polarisation controllers such as BT&DMPC1000 are provided in two input branches to the AND gate. The fixeddelay is provided by a length of polarisation preserving fibre . Thelength of the fibre is chosen so that group delay difference for the twopolarisation eigenmodes of the fibre equals the required delay 1.5 T,corresponding to the time-offset of the marker pulse carried by thepacket. For typical polarisation-preserving fibre, such ashigh-birefringence fibre type HB1500 manufactured by Fibercore Limitedof Chandlers Ford, Hampshire, England, specified as having a beat lengthof less than 2 mm and with packets at a bit rate of 100 Gbit/s, thelength required is less than 30 m, giving a delay of 15 ps. Thepolarisation state of the incoming packet is set to be linear, alignedat 45° to the fibre polarisation axis. This splits the signal into twoorthogonally polarised components that emerge from the fibre with therequired 15 ps time difference. These two orthogonally-polarisedtime-shifted components provide the input signals to the optical ANDgate. The AND gate requires pump light which is coupled into thepolarisation-preserving fibre through a second input branch with anappropriate polarisation.

It is found that with such an AND gate, sharp filtering is required onthe output to separate the AND signal from other features of the output.This however can lead to an undesirable broadening in the output pulseprofile. To avoid this, the output is preferably filtered using anultra-steep edge high rejection fibre Bragg grating filter. Such agrating may be fabricated, for example, in hydrogen loaded (200 Bar)standard telecommunications fibre (Phillips matched-clad) with a nominalcore-cladding index difference of 4.5×10⁻³. A 4 mm long grating may bereplicated using an interfermoneter based on a rectangular silica blockand phase mask, as described in Kashyap R, "Photosensitive opticalfibres: Devices and Applications", Opt. Fibre Technol., 1(1), 17-34,1994. One such filter can give extinctions greater than 64 dB and edgewidths less than 1 nm, and two such filters cascaded with an interposedisolator can give better than 74 dB rejection.

Other methods of distinguishing the marker pulse from the rest of thedata packet include the use of a distinctive intensity, or polarisation.The circuits referenced chip 1 and chip 2 use planar silica delay linesto replicate the marker pulse thereby producing a bit-level clock whichis input to the AND gates of the demultiplexer.

Reference to the packet-level network clock will also be essential atpositions in the network where packets are generated, and as describedbelow it will also be desirable at positions where packets are routed orprocessed in other ways. Preferably the packet-level network clock couldbe derived from adjacent telecommunications equipment that already hasaccess to a suitable distributed clock with sub-nanosecond precision,such as SDH optical line terminations, multiplexers or cross-pointswitches.

Alternatively the clock could be distributed using a separate opticalfibre network, or by using a different wavelength on the same fibre. Afurther possibility is shown in FIG. 17, where the network clock isrecovered directly from the incoming packet stream using an electricalphase-lock loop. The high-frequency response of the photodetector neednot be any greater than the network clock frequency (typically 0.1-1GHz). The photodetector output is amplified, a narrow-band r.f. filteris used to extract the r.f. component at the network clock frequency,and this signal is applied to the reference input of a r.f. phasecomparator. The main input to the comparator is the signal from avoltage-controlled oscillator generating a signal at the network clockfrequency. The output from the phase comparator is used as the errorsignal to drive the voltage-controlled oscillator. The electricalphase-locked loop bandwidth is set to ˜1 MHz or less, sufficient totrack typical phase fluctuations in the incoming packet stream.

Since, preferably, the network nodes will have access to the networkclock, this can be used to simplify and improve the performance ofpacket processing and switching, as the three examples that follow willshow.

The first example is shown in FIG. 18, which is an example of a binaryrouting node in an ultrafast packet network. An incoming cell is to berouted to one of the two output ports of an optoelectronic routingswitch, according to information contained in the cell header. A replicaof the cell is made using a passive optical splitter, and passed to the"routing decision logic unit" which contains both optical and electronicprocessing. The output from this logic unit is used to set theconfiguration of the routing switch. The buffer is used to delay thearrival of the cell until the optical routing switch has been correctlyconfigured for that cell. It is essential that the routing switchchanges configuration only during the "switch band" shown in FIG. 16--ifnot, a cell may be corrupted. Therefore the purpose of the "routingswitch synchronisation" unit in FIG. 18 is to ensure that a signal fromthe decision logic unit will take effect only at the correctinstant--i.e. at the start of the switch band. This is done bysynchronising the routing switch drive signal to the appropriate phasepoint of the network clock. This can be achieved readily usingconventional high-speed digital electronic circuitry.

In the second example, the network clock is used in the electronicprocessing stage of the routing decision logic unit. FIG. 19 is a moredetailed version of FIG. 18, showing an example of a binary routingnode. The optical-processing part of the routing decision logic unitconsists of: i) a first optical AND gate to derive a single ultrashortoptical pulse (called the "synch pulse" in FIG. 4) in precise bit-levelsynchronism with the incoming packet (as described in our co-pendingapplication ref: 80/4850/03) ii) a word-generation stage consisting of apassive optical split-delay-recombine circuit; iii) a second optical ANDgate to perform a binary word-recognition operation. As described inPCT/GB 94/00397, a binary word mismatch (H not equal to W) isrepresented by at least one optical output pulse from the second ANDgate. This optical output is received by a photodetector whoseelectrical output signal (perhaps after amplification) is passed to athreshold detector. This threshold detector is arranged to produce astandardised electrical output pulse if the input from the photodetectorexceeds a certain threshold. This threshold is set somewhat lower thanthe signal level corresponding to a single optical output pulse from thesecond AND gate, and somewhat higher than the noise background. Toimprove the signal-to-noise discrimination of this electronic thresholddetector, it can be advantageous to gate its operation so that it isresponsive only during that fraction of the network clock cycle in whicha legitimate optical signal from the second AND gate might be received.As shown in FIG. 19, a network clock signal can be used to provide thesynchronisation needed for this gate.

A third additional use of the network clock is to help improvesignal-to-noise ratios in optical signal-processing systems. An exampleof this is given in FIG. 20 which shows the arrangement for bit-leveltiming recovery used in FIG. 19. In this example the optical AND gate isthe device described by Nesset et al in our co-pending application, EP94307188.6, and in WO94/21088 ,incorporated herein by reference, whichuses a semiconductor optical amplifier as the nonlinear optical element.It is useful to be able to gate the operation of the semiconductoroptical amplifier so that it is enabled during the time period in whichthe device is needed to perform a processing function (i.e. during thetime when the "photonic network header" shown in FIG. 16 may bepresent), and is disabled during as much as possible of the remainder ofthe network time slot period. This has the advantage that any opticalnoise (such as amplified spontaneous emission) produced by thesemiconductor optical amplifier will be suppressed during the major partof the time slot period, when the device is not performing a usefulprocessing function. The optical AND gate and other optical processingsystems also incorporate several doped-fibre optical amplifiers toamplify the various signals to the required levels, and otherdoped-fibre optical amplifiers will also be required throughout thepacket network to compensate for losses in transmission and switching.These amplifiers all contribute noise due to amplified spontaneousemission, and therefore gating devices such as the semiconductor opticalamplifier can help to control the build-up of noise levels in thenetwork. The semiconductor optical amplifier in FIG. 20 can thereforeperform two useful functions: ultrafast signal processing during the"enabled" period, and noise suppression during the "disabled" period. Arelatively rapid turn-off time can be obtained with these semiconductoroptical amplifiers (i.e. much faster than the carrier lifetime,typically ˜1 ns) when used as the nonlinear element in an optical ANDgate configuration; this is because we use a continuous optical "pump"signal which tends to deplete rapidly the optical gain when theelectrical bias is turned off. Experimentally the turn-on and turn-offtimes for the semiconductor optical amplifier will be mainly determinedby the speed of the electrical drive signals (typically ˜0.1-1 ns). Whenturned off, the semiconductor optical amplifier acts as a very effectivelight absorber, typically giving an optical on:off intensity ratio ashigh as ˜40 dB. Therefore, if the semiconductor optical amplifier isturned off for ˜90% of the network clock period, the averaged opticalnoise suppression can be ˜10 dB.

Above, we described possible methods for recovering the packet-levelnetwork clock at intermediate network nodes. Another possible approachis to generate an incomplete clock by deriving a timing signal fromindividual packets (e.g. the optical "synch pulse" shown in FIG. 19).This clock is incomplete because no signal is obtained when a times slotis unoccupied. This incomplete clock may be satisfactory for somepurposes e.g. synchronisation of simple binary routing switches(satisfactory because a momentary loss of synchronisation may not matterif no packet is present). In general, however, the complete networkclock may be needed to synchronise more complex routing switches (suchas the packet-merging switch described in our co-pending application EP94306015.2, incorporated herein by reference, page 8 and FIG. 15) andfor gating active devices to improve noise immunity.

                  TABLE    ______________________________________    PF ROUTING    Current node               Current Node    Con-                Preferred                               Con-             Preferred    figuration            ΔR                  ΔC                        Path   figuration                                        ΔR                                            ΔC                                                Path    ______________________________________    δR = +1            <0    <0    random δR = +1                                        <0  <0  down    δC = +1 0     down   δC = -1                                            0   down                  >0    down                >0  random            0     <0    right           0   <0  down                  0     --                  0   --                  >0    down                >0  left            >0    <0    right           >0  <0  random                  0     right               0   left                  >0    random              >0  left    δR = -1            <0    <0    right  δR = -1                                        <0  <0  random    δC = +1 0     right  δC = -1                                            0   left                  >0    random              >0  left            0     <0    right           0   <0  up                  0     --                  0   --                  >0    up                  >0  left            >0    <0    random          >0  <0  up                  0     up                  0   up                  >0    up                  >0  random    ______________________________________

We claim:
 1. A method of routing a packet at a routing node on an optical network, comprising the steps of:carrying out in the optical domain a logic operation on an address word carried in a packet header and a discriminator word chosen from a set of discriminator words smaller in number than the set of address words for said optical network or domain of said optical network in which said node is located; and routing said packet based on the direct result of the logic operation.
 2. A method according to claim 1, wherein the address word and the discriminator word are both chosen from the subset of n-bit binary words having the property that for any two words A, B, AxB=0 only if A=B and AxB=1 otherwise, where AxB denotes the Boolean operation ##EQU3##
 3. A method according to claim 1, wherein the logic operation is a bit-wise AND operation on the address word and the discriminator word.
 4. A method according to claim 1, wherein in making a single routing decision the routing node carries out two or more logic operations on the address word and on a respective two or more discriminator words.
 5. A method according to claim 4, wherein one of the said two or more logic operations is carried out conditionally depending upon the result of a preceding logic operation.
 6. A method according to claim 1, further comprising carrying out an additional logic operation on the address word and on a respective additional discriminator word for determining whether the packet is addressed to a remote region of the network, and when the packet is so addressed, routing the packet directly towards the said region.
 7. A method according to any one of the preceding claims, wherein the header of each packet includes an address comprising a plurality of address words corresponding to different sub-fields of the address.
 8. A method according to claim 7, in which the address word and the discriminator word are both chosen from the subset of n-bit binary words having the property that for any two words A, B, AxB=0 only if A=B and AxB=1 otherwise, where AxB denotes the Boolean operation and in which both the subfield words and the complete address formed by concatenating the sub-field words are members of the said subset of binary words.
 9. A method according to claim 7, wherein the different sub-fields correspond to different respective levels of a hierarchy of addresses, an address at one level corresponding to a domain encompassing a plurality of addresses at the next respective level, and so on.
 10. A method according to claim 1, wherein said optical network includes a plurality of routing nodes organized in a 2-connected topology, each routing node having two inputs and two outputs.
 11. A method according to claim 10, wherein said 2-connected topology comprises a picket fence topology in which said routing nodes are connected together as a regular array of rows and columns and in which the nodes at the ends of adjacent rows are connected to each other and the nodes at the ends of adjacent columns are connected to each other to thereby provide bi-directional links at the periphery of said optical network.
 12. A method according to claim 1, wherein said optical network has a generally one-dimensional topology.
 13. A method according to claim 1, wherein said optical network has a dual-bus or dual ring topology.
 14. A node for routing a packet carried on an optical network comprising:a routing decision unit arranged to carry out in the optical domain a logic operation on an address word carried in the header of the packet and a predetermined discriminator word; and a switch responsive to the routing decision unit and arranged to route the packet in different directions depending on the result of the logic operation.
 15. A node according to claim 14, further comprising an optical address recognition unit (ARU) connected to receive incoming packets and arranged to determine whether said packet is addressed to the said node, said packet being passed on to the routing decision unit only when determined not to be addressed to the said node.
 16. A node according to claim 15, wherein the ARU includes an optical AND gate arranged to carry out a bit-wise AND operation on said address word and a target word characteristic of the address of the node.
 17. A node according to claim 14, wherein said routing decision unit includes an optical AND gate arranged to carry out a bit-wise AND operation on the address word and the discriminator word.
 18. An optical network including a plurality of routing nodes according to claim 14, different nodes including routing decision units programmed with different respective discriminator words.
 19. A network according to claim 18, wherein said optical network has a 2-connected topology in which each routing node has two inputs and two outputs.
 20. A network according to claim 18, wherein said optical network has a one-dimensional topology.
 21. An optical network comprising a plurality of nodes, each node having a different respective address, and each node includinga routing decision unit programmed with a discriminator word chosen from a set of discriminator words smaller than the number of address words and arranged to carry out a logic operation in the optical domain on said address word and the respective discriminator word; and a switch responsive to the routing decision unit and arranged to route respective packets in different directions depending on the result of the logic operation.
 22. A method of routing a packet at a node of an optical network, comprising the steps of:logically combining in the optical domain address data for said packet and discriminator data for discriminating between address data for which a first routing direction is appropriate and address data for which a second routing direction is appropriate; and routing said packet in one or the other of the first and second routing directions based on the result of the logical combination.
 23. A method according to claim 22, wherein the address data comprises at least two subfields, each subfield corresponding to a different respective level of a hierarchy of addresses.
 24. A method according to claim 22, wherein the step of logically combining uses AND logic.
 25. A node for routing a packet on an optical network, comprising:logic circuitry for logically combining in the optical domain address data for said packet and discriminator data for discriminating between address data for which a first routing direction is appropriate and address data for which a second routing direction is appropriate; and a switch for routing said packet in one or the other of the first and second routing directions based on the result of the logical combination.
 26. A node according to claim 25, wherein said logic circuitry comprises an optical AND logic circuit.
 27. A node according to claim 25, further comprising:an address recognition unit connected to receive said packet and configured to use the address data for said packet to determine whether said packet is addressed to said node, said address recognition unit passing said packet to said logic circuitry only when said packet is determined not to be addressed to said node. 